1. Field of the Invention
The invention in general relates to electronic memories, and more particularly to such a memory that applies the full programming voltage across the memory element during the read and write functions.
2. Statement of the Problem
It is well-known that ferroelectric materials are capable of retaining a polarization which can be used to store information in a non-volatile memory. For example, if a strong enough electric field is placed across a ferroelectric capacitor, when the electric field is removed, a polarization in the direction of the field remains. If the field is placed across the same capacitor in the opposite direction, when the field is removed, a polarization in the opposite direction remains. Electronic circuits have been designed to associate the polarization in one direction with a digital logic "1" state, and polarization in the opposite direction with a logic "0" state. Some examples of such memories circuits are described in U.S. Pat. No. 4,809,225 issued to Klaus Dimmler and S. Sheffield Eaton, Jr., U.S. Pat. No. 4,853,893 issued to S. Sheffield Eaton, Jr. and Michael Parris, U.S. Pat. No. 4,873,664 issued to S. Sheffield Eaton, Jr., U.S. Pat. No. 4,888,733 issued to Kenneth J. Mobley, U.S. Pat. No. 893,272 issued to S. Sheffield Eaton, Jr., Douglas Butler, and Michael Parris, U.S. Pat. No. 4,910,708 and U.S. Pat. No. 4,914,627 issued to S. Sheffield Eaton, Jr., U.S. Pat. No. 5,010,518 issued to Haruki Toda, U.S. Pat. No. 5,038,323 issued to Leonard J. Schwee, U.S. Pat. No. 5,086,412 issued to James M. Jaffe and Norman E. Abt, U.S. Pat. No. 5,198,706 issued to Andreas G. Papaliolios, and U.S. Pat. No. 5,406,510 issued to Takashi Mihara, Carlos A. Paz De Araujo, and Larry D. McMillan. All these patents utilize memory array structures including memory cells arranged in rows and columns, each memory cell including at least one transistor having a gate and a pair of source/drains, a capacitor having a pair of plate electrodes, and the memory also including in some form plate lines connected to one plate of the capacitor in each cell, bit lines connected to the other plate of the capacitor through the transistor, word lines connected to the control gate of the transistor, and sense amplifiers. Each is characterized by the bit line having a certain capacitance, which can be represented by a bit line "capacitor". Each of these memories is read by placing a programmed voltage sufficient to switch the ferroelectric capacitor across the ferroelectric capacitor. In each memory, the transistor is closed during a read operation, thereby placing the programmed voltage across the combination of the ferroelectric capacitor and the bit line capacitor. If the ferroelectric capacitor switches, a different voltage appears on the bit line than if the ferroelectric capacitor does not switch. The sense amplifier senses the difference and amplifies it to provide the output data signal.
In the read operation of all the above devices, the bit line voltage is allowed to float. This results in the ferroelectric capacitor and the bit line capacitor forming a capacitive divider, with part of the programmed voltage appearing across the ferroelectric capacitor and part on the bit line. Since the voltage required to switch the ferroelectric capacitor is just a little less than the nominal operating voltage of these circuits, i.e. three to five volts, most of the voltage must appear across the ferroelectric capacitor to facilitate the possibility of ferroelectric switching, and therefore, the bit line capacitance must be large in comparison to the ferroelectric capacitance. However, the bit line capacitance cannot be so large that the bit line voltage is too small to be sensed reliably by the sense amp. These opposing constraints severely limit the design possibilities in a ferroelectric memory. For example, the small voltage requires very sensitive sense amplifiers, and designs that keep noise to a minimum. As another example, the requirements of bit line capacitance essentially determines the number of cells that can be connected along a single bit line. Further, the opposing constraints lead to ferroelectric memory designs that are unreliable, since if the tolerances are off just a small amount in either direction, the memory does not work. Thus, a ferroelectric memory in which the voltage across the ferroelectric capacitor was independent of the bit line parameters would be highly desirable.
3. Solution to the Problem
The present invention solves the above problem by driving the bit line with a voltage that can vary. The invention provides a feed back connection from the bit line to the circuit that drives the plate line, and the plate line driving circuit using the feed back to drive the plate line to the voltage that creates the full programming voltage across the ferroelectric capacitor, no matter what the voltage is on the bit line. This allows the bit line capacitance to be tailored to other design goals. For example, the bit line capacitance can be closer to, or even equal to the ferroelectric capacitance, increasing the bit line voltage and therefore increasing the signal to noise ratio at the sense amp. This makes the design much less susceptible to tolerance variations and other defects, and therefor increases yield.
The invention provides ferroelectric memory comprising: a memory cell including a ferroelectric memory element capable of taking on a first polarization state corresponding to a logic "1" state and a second polarization state corresponding to a logic "0" state, the memory cell including at least one electrical; a drive circuit having an output for applying an electrical voltage to the terminal of the ferroelectric element; a feedback circuit for providing a feedback signal from the memory cell to the drive circuit; and the drive circuit including an amplifier circuit for adjusting the signal output to the terminal to maintain a predetermined voltage across the memory cell. Preferably, the amplifier circuit includes an operational amplifier having an inverting input, a non-inverting input, and an output, the operational amplifier output comprising the output for applying an electrical voltage to the terminal. Preferably, the ferroelectric memory element comprises a ferroelectric capacitor having a plate line connected to one side of the capacitor and a bit line connected to the other side of the capacitor. Preferably, the output of the operational amplifier is connected to the plate line and the feedback circuit is connected between the bit line and one of the inputs of the operational amplifier. Preferably, the bit line is connected to the non-inverting input, and the plate line is connected to the inverting input. Preferably the memory further includes a transistor connecting the bit line to the other side of the capacitor, a source of a variable voltage, a source of a constant voltage, a first resistor, a second resistor, a third resistor and a fourth resistor, the first resistor connected between the source of variable voltage and the non-inverting input, the second resistor connected between the bit line and the non-inverting input, the third resistor connected between the source of a constant voltage and the inverting input, and the fourth resistor connected between the plate line and the inverting input. Preferably, the varying voltage can take on a value representative of a logic "0" and a value representative of a logic "1", and the constant voltage is half way between the logic "0" voltage and the logic "1" voltage. Preferably, the first resistor has the value "r", the second resistor has the value "a.times.r", the third resistor has the value "R", and said fourth resistor has the value "a.times.R", where 1.ltoreq.a.ltoreq.3. Preferably, the feedback circuit includes a buffer amplifier.
In another aspect the invention provides an integrated circuit memory comprising: a memory cell; a drive circuit for applying a voltage to the memory cell; and a connecting circuit electrically connecting the memory cell and the drive circuit, the connecting circuit including a buffer amplifier. Preferably, the memory cell includes a ferroelectric memory element.
In a further aspect, the invention provides an integrated circuit memory comprising: a memory cell; a drive circuit for applying a voltage to the memory cell, the drive circuit including an operational amplifier. Preferably, the memory cell includes a ferroelectric memory element. Preferably, the ferroelectric memory element comprises a ferroelectric capacitor, and the operational amplifier includes an output connected to one side of the ferroelectric capacitor. Preferably, the operational amplifier includes an input and the other side of the ferroelectric capacitor is connected to the input of the operational amplifier. Preferably the integrated circuit includes a bit line connected to the memory cell and a plate line connected to the memory cell, the operational amplifier includes two inputs, and the bit line is connected to one of the operational amplifier inputs and the plate line is connected to the other of the operational amplifier inputs. Preferably, the integrated circuit includes a source of a constant voltage and a source of a variable voltage, the operational amplifier includes two inputs, the source of a constant voltage is connected to one of the operational amplifier inputs, and the source of a variable
The invention not only frees up the bit line design criteria, but also ensures that the full programming voltage always appears across the ferroelectric capacitor. Thus, the memory will essentially automatically adjust for variances in manufacturing tolerances that could make prior art designs inoperable. Numerous other features, objects and advantages of the invention will become apparent from the following description when read in conjunction with the accompanying drawings.